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| www.ams.com high performance needs great design . d atasheet: AS8525 lin transceiver with voltage reg ulators, programmable gain high side amplifier, and voltage attenuator please be patient while we update our brand image as austriamicrosystems and taos are now ams.
AS8525 lin transceiver with voltage regu lators, programmable gain high side amplifier, and voltage attenuator www.ams.com/AS8525 revision 2.3 1 - 37 1 general description the AS8525 is a companion ic for automotive battery sensor systems for both low-side and high-side current sensing applications. the device provides two regulated 3.3v (or 5v) supplies from the battery supply, attenuated battery voltage in differential form, and amplified version of a high-side current-sense element?s voltage with a translated common-mode voltage. the device also communicates the system output to a lin bus. AS8525 is designed in a high-voltage 0.35m cmos process and packaged on qfn-32. 2 key features ?? operating voltage 4.3v to 18v, max. 42v for 500 ms ?? two linear low-drop voltage regulators: vcc = 3.3v or 5v as a factory programming option with 50ma drive capability ?? typical 50a quiescent current in standby mode ?? typical 35a quiescent current in sleep mode ?? precision voltage attenuator with power down facility - 0.2% ratio drift accuracy and disable ?? precision fully-differential programmable gain amplifier (pga) - high-voltage to low-voltage common-mode translation - gain steps 5, 25, 50, 100 ?? lin bus transceiver - load independent slew control conforming to lin 2.1 - short circuit protection - tx time out fail safe feature - over temperature warning and shut down ?? power-on reset with otp adjustable reset timeout and brown- out detection ?? over temperature warning & shutdown functions ?? operating modes: normal, standby, sleep, temporary shut down ?? microcontroller 4-wire interface ?? rc oscillator and programmable timer ?? optional window watchdog in normal mode and time-out watchdog in standby mode ?? 8 backup registers to store mcu data during vcc shut down ?? load dump protection for all battery supplied pins, lin bus pin and enable pin ?? internal reverse polarity protection (up to -27v) for all battery- sensing pins and lin bus pin ?? chip id for traceability ?? -40oc to +125oc ambient operating temperature ?? 32-pin qfn (5x5) package 3 applications the AS8525 is suitable for lin networked 14v battery sensor slaves for current measurement in positive battery power rail (high side) or in minus rail (pga is left un-used in that case). the device is also ideal for general purpose system basis chip for actuator lin slaves with battery voltage sensing and actuator high side current sensing. www.ams.com/AS8525 revision 2.3 2 - 37 AS8525 datasheet - applications figure 1. AS8525 block diagram ldo lin wakeup receiver vsup transmitter lin transceiver attenuator pga with common-mode translation + vsup en rx tx hrshl hrshh vbat vss1 vbat_div lrshl lrshh lin sdi sdo sclk cs reset vcc - avcc vbg_in avcc vbat_divn vsup2 vss2 clk int men aldo ldo window watchdog timeout watchdog reset por- vcc mode control por- vsup temp limiter signal path mode control otp memory slew control vcmref generator + - + - g chp control registers diagnostic registers backup registers AS8525 www.ams.com/AS8525 revision 2.3 3 - 37 AS8525 datasheet - contents contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 applications................................................................................................................ ............................................................... 1 4 pin assignments ............................................................................................................. .......................................................... 5 4.1 pin descriptions.......................................................................................................... .......................................................................... 5 5 absolute maximum ratings .................................................................................................... .................................................. 7 6 electrical characteristics.................................................................................................. ......................................................... 8 6.1 characteristics of digital inputs and outputs ............................................................................. .......................................................... 8 6.2 detailed system and block specifications .................................................................................. ......................................................... 9 6.2.1 programmable gain amplifier (pga)....................................................................................... .................................................. 10 6.2.2 vcmref generator ........................................................................................................ .......................................................... 11 6.2.3 voltage attenuator ...................................................................................................... ............................................................... 11 6.2.4 voltage regulators (ldo & aldo) ......................................................................................... .................................................. 11 6.2.5 lin transceiver ......................................................................................................... ................................................................ 12 6.2.6 tx timeout watchdog ..................................................................................................... .......................................................... 13 6.2.7 temperature limiter ..................................................................................................... ............................................................. 13 6.2.8 other modules ........................................................................................................... ................................................................ 14 6.2.9 4-wire serial port interface ............................................................................................ ........................................................... 15 6.3 timing diagrams ........................................................................................................... ..................................................................... 16 7 detailed description........................................................................................................ ........................................................ 17 7.1 programmable-gain amplifier (pga) / current-sense amplifier (csa) ......................................................... .................................... 17 7.2 voltage attenuator ........................................................................................................ ...................................................................... 17 7.3 voltage regulators (ldo & aldo) ........................................................................................... ......................................................... 17 7.4 lin transceiver ........................................................................................................... ....................................................................... 18 7.5 temperature monitor / limiter............................................................................................. ................................................................ 18 7.6 vsup under-voltage reset .................................................................................................. ............................................................. 18 7.7 reset..................................................................................................................... ........................................................................... 18 7.8 vcc under-voltage reset................................................................................................... ............................................................... 19 7.9 window watchdog (wwd) ..................................................................................................... ............................................................ 19 7.10 timeout watchdog (twd) ................................................................................................... ............................................................. 19 8 application information ..................................................................................................... ...................................................... 20 8.1 operating modes and states................................................................................................ .............................................................. 20 8.1.1 normal mode ............................................................................................................. ................................................................ 20 8.1.2 standby mode............................................................................................................ ................................................................ 20 8.1.3 sleep mode.............................................................................................................. .................................................................. 20 8.1.4 temporary shutdown mode ................................................................................................. ..................................................... 20 8.1.5 thermal shutdown mode................................................................................................... ........................................................ 20 8.2 state transition diagram.................................................................................................. .................................................................. 21 8.3 initialization............................................................................................................ ............................................................................. 23 8.4 wake-up................................................................................................................... .......................................................................... 24 8.5 lin bus transceiver ....................................................................................................... ................................................................... 24 8.5.1 transmit mode........................................................................................................... ................................................................ 24 8.5.2 receive mode............................................................................................................ ................................................................ 24 www.ams.com/AS8525 revision 2.3 4 - 37 AS8525 datasheet - contents 8.6 rx and tx interface ....................................................................................................... .................................................................... 25 8.6.1 input tx ................................................................................................................ ..................................................................... 25 8.6.2 output rx ............................................................................................................... ................................................................... 25 8.7 mode input en............................................................................................................. ..................................................................... 26 8.8 4-wire spi interface ...................................................................................................... ..................................................................... 28 8.8.1 spi frame............................................................................................................... ................................................................... 28 8.8.2 write command........................................................................................................... .............................................................. 28 8.8.3 read command............................................................................................................ ............................................................. 29 8.8.4 timing .................................................................................................................. ...................................................................... 30 8.9 configuration and diagnostic registers .................................................................................... ......................................................... 31 8.9.1 register definitions.................................................................................................... ................................................................ 32 9 package drawings and markings ............................................................................................... ............................................ 34 10 ordering information....................................................................................................... ...................................................... 36 www.ams.com/AS8525 revision 2.3 5 - 37 AS8525 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin name pin number pin type description nc 1 not connected vbat 2 analog input battery voltage input hrshh 3 battery-side connection to high-side current-sense element vsup2 4 supply supply input for the high-side amplifier hrshl 5 analog input load-side connection to high-side current-sense element nc 6 not connected vbat_div 7 analog output attenuated battery voltage output (differential) vbat_divn 8 lrshl 9 gained current-sense element voltage output with translated common-mode voltage (differential) lrshh 10 3 2 1 4 5 6 7 8 9 10 11 17 16 15 14 13 12 18 19 20 21 22 23 24 25 AS8525 (qfn-32) 28 27 26 vsup lin vbat hrshl hrshh en vcc tx rx reset clk men int lrshh lrshl vbat_div vbg_in cs sdo sdi sclk 29 32 31 30 avcc vbat_divn vsup2 vsup vss1 vss2 www.ams.com/AS8525 revision 2.3 6 - 37 AS8525 datasheet - pin assignments vbg_in 11 analog input low noise bandgap reference voltage input nc 12 not connected int 13 digital input reference input for time-out watchdog in the device standby mode men 14 digital i/o with pull-down enable input for analog signal paths in the device standby mode clk 15 digital input with pull-down chopper clock input reset 16 digital output reset output (active low) sdi 17 digital input with pull-down serial data in sclk 18 serial clock sdo 19 digital output / tristate serial data out cs 20 digital input with pull-up chip select rx 21 digital i/o with pull-up lin transceiver receive pin tx 22 lin transceiver transmit pin avcc 23 supply regulated 3.3v(/otp selectable 5v) regulated output supply-2 for loads up to 50ma note: the otp selection option is common for vcc & avcc vcc 24 regulated 3.3v(/otp selectable 5v) regulated output supply-1 for loads up to 50ma en 25 digital input with pull-down enable input vsup 26 supply supply input from battery (through external reverse polarity protection device) 27 lin 28 analog input / output lin bus nc 29 not connected vss1 30 ground ground vss2 31 ground (vcc and avcc are generated with reference to this ground) nc 32 not connected table 1. pin descriptions pin name pin number pin type description www.ams.com/AS8525 revision 2.3 7 - 37 AS8525 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 8 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings symbol parameter min typ max units comments vsup supply voltages -0.3 42 v maximum allowed potential difference between any two pins in the set hrshh, hrshl and vsup2 is 0.3v vsup2 -27 42 vbat, hrshh, hrshl battery voltage inputs -27 42 v en enable input -0.3 42 v vcc, avcc regulated output supplies -0.3 7 v lin lin bus -27 40 v analog & digital inputs and outputs -0.3 7 v i scr input current (latchup immunity) -100 100 ma norm: aec-q100 esd electrostatic discharge 1 norm: aec-q100 1. esd human body model: r=1500 and c=150pf 2 kv for vcc, avcc, tx, rx, reset, cs, sclk, sdo, sdi, en, vbat_div, vbat_divn, lrshh, lrshl, vbg_in, clk, int, men 4 vsup, vsup2, vbat, hrshh, hrshl 8 lin to vss1, hbm model 6 lin to vss1, iec6100-4-2 0.5 lin to vss1, cdm 0.1 lin to vss1, mm p tot total operating power dissipation (all supplies and outputs) 1w qfn 32 in still air, soldered on jedec standard board @125o ambient, static operation = no time limit r o package thermal resistance 25 oc/w t stg storage temperature -55 +150 oc t body package body temperature +260 oc the reflow peak soldering temperature (body temperature) is specified according ipc/jedec j-std-020c ?moisture/reflow sensitivity classification for non hermetic solid state surface mount devices?. humidity non-condensing 5 85 % www.ams.com/AS8525 revision 2.3 8 - 37 AS8525 datasheet - electrical characteristics 6 electrical characteristics 6.1 characteristics of digi tal inputs and outputs all pull-up, pull-downs have been implemented with active dev ices. rx, sdo, reset have been measured with 100pf load. table 3. operating conditions symbol parameter conditions min typ max units vsup supply voltages 3.3v regulators option after power-on reset 4.3 18 v 3.3v regulators option for power-on reset 6 5v regulators option 6 vsup2 4.5 18 v vbat, hrshh, hrshl battery voltage inputs 4.5 18 v vhiside difference between any two pins in the set hrshh, hrshl and vsup2 0.2 v lin lin bus 018v en enable input 018v vcc, avcc regulated output supplies 3.3v ldo supply option 0 3.6 v vcc difference in regulated supplies 0.2 v vbg_in bandgap reference input 01.32v analog & digital inputs and outputs 3.3v ldo supply option 0 3.6 v t amb ambient temperature maximum junction temperature (t j )=150oc -40 +125 oc i sup supply current though the two regulators are individually capable of 50ma, the total current is limited. 65 ma table 4. characteristics of digital inputs and outputs symbol parameter conditions min typ max units en input v ih high level input voltage 0.8*vcc v v il low level input voltage 0.2*vcc v i leak input leakage current en=vss -1 +1 a i pd_en pull down current en=vcc=5v 30 100 a tx, cs, int inputs v ih high level input voltage 0.8*vcc v v il low level input voltage 0.2*vcc v i leak input leakage current tx=vcc -1 +1 a ipu pull up current tx,cs, intn pulled down to vss -30 -100 a sdi, sclk, clk, men inputs v ih high level input voltage 0.8*vcc v v il low level input voltage 0.2*vcc v i leak input leakage current -1 +1 a i pd_spi pull down current sdi, sclk, clk, men pulled up to vcc 30 100 a www.ams.com/AS8525 revision 2.3 9 - 37 AS8525 datasheet - electrical characteristics 6.2 detailed system and block specifications rx output v oh high level output voltage v v ol low level output voltage i out = 1ma, vsup 6v vss+0. 4 v i pu_reset pull-up current pulled down to vss -100 a sdo, reset output v oh high level output voltage v v ol low level output voltage vsup 6v vss+0. 4 v table 5. system specifications symbol parameter conditions min typ max units ivsupnom current consumption normal mode no load on vcc, avcc, lin bus in recessive state, current sense channel on 850 a ivbatnom 60 ivsup2nom current sense channel on 600 ivsupstdby current consumption standby / sleep mode no load on vcc, avcc, lin bus in recessive state 40 a ivsupsleep 30 ivbatoff voltage sense channel off 1 ivsup2off current sense channel off 1 table 4. characteristics of digital inputs and outputs (continued) symbol parameter conditions min typ max units www.ams.com/AS8525 revision 2.3 10 - 37 AS8525 datasheet - electrical characteristics 6.2.1 programmable gain amplifier (pga) table 6. programmable gain amplifier (pga) symbol parameter conditions min typ max units g1 gain dc gain 5 v/v g2 25 g3 50 g4 100 v in_amp input signal range v(hrshh)-v(hrshl) gx represents typical gain value (x=1,2,3,4) after offset trimming 0.18*5/ gx v v icm_amp input common-mode voltage v(hrshh), vsup2 4.5 12 18 v v ocm_amp output common-mode voltage when avcc=3.3v only for information 1.5 1.65 1.8 v when avcc=5v only for information 2.3 2.5 2.7 p1,g gain error temperature: -40 to +125oc @ vsup2 = 18v post system calibration 0.5 % p2,g at room temperature v(hrshh), vsup2=12v without system calibration 5 % t settle_amp time for settling to within 0.05% final value includes the settling of chopper 45 s f -3db amp 3-db bandwidth g1 650 khz g2 250 g3 150 g4 75 v ndin_amp input referred thermal noise density (rms) this excludes 1/f noise guaranteed by design 35 nv/ hz thd amp total harmonic distortion till 500hz single-ended sinusoidal inputs (after offset trimming). guaranteed by design 70 db c l_amp load capacitance single ended (includes the capacitance presented by the pad and pin of the host chip) 100 pf v bg_amp bandgap reference voltage external low noise reference 1.176 1.2 1.224 v v ndbg_amp bandgap reference thermal noise density when noise bandwidth < signal bandwidth, take it as 200nv/ hz (noise bandwidth / signal bandwidth) 200 nv/ hz v osin_amp input referred offset before trimming refers to the standalone amplifier without chopper stabilization 37.5 mv v osint_amp input referred offset after trimming refers to the standalone amplifier without chopper stabilization; only at room temperature 1.5 mv www.ams.com/AS8525 revision 2.3 11 - 37 AS8525 datasheet - electrical characteristics 6.2.2 vcmref generator 6.2.3 voltage attenuator 6.2.4 voltage regulators (ldo & aldo) table 7. vcmref generator symbol parameter conditions min typ max units v cmref_amp common-mode reference voltage when avcc=3.3v 1.55 1.65 1.75 v when avcc=5v 2.35 2.5 2.65 table 8. voltage attenuator symbol parameter conditions min typ max units rdiv division ratio 481 v/v v bat input voltage range/ battery voltage range 4.5 12 18 v p,rdiv ratio error at room temperature, v bat =12v 1 % dt1,rdiv ratio drift (w.r.t temperature) temperature: -25 to +65oc @vbat = 12v 0.05 % dt2,rdiv temperature: -40 to +125oc @vbat = 12v 0.2 dv1,rdiv ratio drift (w.r.t v bat ) vbat: 11 to 13 v @ temperature = 27oc 0.05 % dv2,rdiv vbat: 6 to 18 v @ temperature = 27oc 0.2 table 9. voltage regulators (ldo & aldo) symbol parameter conditions min typ max units vsup input supply voltage 3.3v option 4.3 12 18 v vcc avcc output voltage range 3.3v option 3.15 3.3 3.45 v i load ldo load current 50 ma aldo load current 0.01 50 ma icc_sh output short circuit current normal mode 250 ma dvcc1 line regulation vcc / vsup for vsup range 8 mv/v loreg load regulation vcc / iccn (0.5ma < i load < 50ma) 1mv/ma cl1 output capacitor1 ldo electrolytic 2.2 10 f esr1 110 cl2 output capacitor2 ldo ceramic 100 220 nf esr2 0.02 1 cl1 output capacitor1 aldo electrolytic 2.2 5 f esr1 110 cl2 output capacitor2 aldo ceramic 100 220 nf esr2 0.02 1 www.ams.com/AS8525 revision 2.3 12 - 37 AS8525 datasheet - electrical characteristics 6.2.5 lin transceiver table 10. dc electrical characteristics symbol parameter conditions min typ max units driver i bus_lim current limitation in dominant state lin=vsup_max 40 120 200 ma lin_v ol output voltage bus (dominant state), i lin =40ma (short-circuit cond ition tested at v ol =2.5v) 2v pull-up resistor normal mode (recessive bus level on tx pin) 20 40 60 k i bus_leak_rec driver off; 7.3v < vsup < 18; 8v < vbus < 18, vsup < vbus < 1.08 * vsup (to be tested at vbus=18v) 20 a receiver i bus_leak_dom input leakage current at receiver driver off; vbus=0v; vsup=12v; vcc=5v -1 ma i bus_no_gnd vss=vsup; vsup=12v; 0v < vbus < 18v, vcc=5v (to be tested at vbus=18v) -1 1 ma i bus_no_bat vsup=vss; 0v < vbus < 18v, vcc=vss (to be tested at vbus=18v) 100 a v bus_dom 0.4 vsup v bus_rec 0.6 vsup v bus_cnt v bus_cnt = (v th_dom + v th_rec )/2 1 1. v th_dom : receiver threshold of the recessive to dominant lin bus edge, v th_rec : receiver threshold of the dominant to recessive lin bus edge 0.475 0.525 vsup v hys v hys = (v th_dom ? v th_rec ) 1 0.05 0.175 vsup table 11. ac electrical characteristics symbol conditions min typ max units lin driver, bus load conditions (c bus ; r bus ): 1nf; 1k / 6.8nf; 660 / 10nf; 500 d1 worst case 20kbps transmission v th_rec (max) = 0.744 x vsup; v th_dom (max) = 0.581 x vsup; vsup = 6.0v...18v; t bit = 50 s; d1 = t bus_rec (min) / (2 x t bit ) otp selection = high slew mode 0.396 d2 worst case 20kbps transmission v th_rec (min) = 0.422 x vsup; v th_dom (min) = 0.284 x vsup; vsup = 6v...18v; t bit = 50 s; d2 = t bus_rec (max) / (2 x t bit ) otp selection = high slew mode 0.581 d3 worst case 10.4kbps transmission v th_rec (max) = 0.778 x vsup; v th_dom (max) = 0.616 x vsup; vsup = 6.0v...18v; t bit = 96 s; d3 = t bus_rec (min) / (2 x t bit ) otp selection = low slew mode 0.417 www.ams.com/AS8525 revision 2.3 13 - 37 AS8525 datasheet - electrical characteristics 6.2.6 tx timeout watchdog 6.2.7 temperature limiter d4 worst case 10.4kbps transmission v th_rec (min) = 0.389 x vsup; v th_dom (min) = 0.251 x vsup; vsup = 6v...18v; t bit = 96 s; d4 = t bus_rec (max) / (2 x t bit ) otp selection = low slew mode 0.59 t dlr vcc=5v; propagation delay bus dominant to rx low 6 s t dhr vcc=5v; propagation delay bus dominant to rx high 6 s t rs receiver delay symmetry -2 2 s t wake wake-up delay time 30 150 s t sln transition from standby mode to normal mode (clock frequency is 128khz 25%) 4 clock cycles t nsl transition from standby mode to normal mode (clock frequency is 128khz 25%) 6 clock cycles t rec_deb receiver de-bounce time 0.6 1 s c int internal capacitance of the lin node 250 pf table 12. tx timeout watchdog symbol parameter conditions min typ max units t lin_wdog time out period for the dominant state 0.5 1 2 s table 13. temperature limiter symbol parameter conditions min typ max units t sd shut down temperature junction temperature 155 170 185 oc t otset over-temperature warning junction temperature 142 157 172 oc t ret return temperature junction temperature 125 140 155 oc table 11. ac electrical characteristics (continued) symbol conditions min typ max units www.ams.com/AS8525 revision 2.3 14 - 37 AS8525 datasheet - electrical characteristics 6.2.8 other modules table 14. other modules symbol parameter conditions min typ max units vuvr_off vcc under-voltage threshold off (default) rising edge of vcc 2.55 2.95 v vuvr_on vcc under-voltage threshold on (default) falling edge of vcc 2.3 2.7 v vuvr1_off vcc under voltage threshold off (factory option) rising edge of vcc 3.0 3.4 v vuvr1_on vcc under voltage threshold on (factory option) falling edge of vcc 2.75 3.15 v vuvr2_off vcc under voltage threshold off (factory option) rising edge of vcc 3.5 3.9 v vuvr2_on vcc under voltage threshold on (factory option) falling edge of vcc 3.25 3.65 v vuvr3_off vcc under-voltage threshold off (factory option) rising edge of vcc 4.0 4.4 v vuvr3_on vcc under voltage threshold on (factory option) falling edge of vcc 3.75 4.15 v vhyst_vcc hysteresis of under-voltage threshold on/ off vcc for all otp options 0.1 0.25 0.4 v t rr glitch filter on vcc under-voltage detection see reset functionality (page 18) 4s vsuvr_off vsup under-voltage threshold off rising edge of vsup 5.1 v vsuvr_on vsup under-voltage threshold on falling edge of vsup 3.8 v wd_tcl wwd non-service time (factory option) reset will be generated 0-75 0-100 0-125 ms wd_tsv wwd service time (factory option) reset will not be generated 75-150 100-200 125-250 ms wd_tcl1 wwd non-service time (factory option) reset will be generated 0-60 0-80 0-100 ms wd_tsv1 wwd service time (factory option) reset will not be generated 60-120 80-160 100-200 ms wd_tcl2 wwd non-service time (factory option) reset will be generated 0-45 0-60 0-75 ms wd_tsv2 wwd service time (factory option) reset will not be generated 45-90 60-120 75-150 ms wd_tcl3 wwd non-service time (factory option) reset will be generated 0-150 0-200 0-250 ms wd_tsv3 wwd service time (factory option) reset will not be generated 150-300 200-400 250-500 ms wd_tcl4 wwd non-service time (factory option) reset will be generated 0-120 0-160 0-200 ms wd_tsv4 wwd service time (factory option) reset will not be generated 120-240 160-320 200-400 ms wd_tcl5 wwd non-service time (factory option) reset will be generated 0-90 0-120 0-150 ms wd_tsv5 wwd service time (factory option) reset will not be generated 90-180 120-240 150-300 ms wd_t twd service time t is configured through spi 0.75*t t 1.25*t s t res reset period min = -25% and max = +50% 6 8 12 ms t shd temporary shutdown reset active time 0.1 1 s www.ams.com/AS8525 revision 2.3 15 - 37 AS8525 datasheet - electrical characteristics 6.2.9 4-wire serial port interface table 15. 4-wire serial port interface symbol parameter conditions min typ max units general br spi bit rate 250 kbps t sclkh clock high time 2 s t sclkl clock low time 2 s write timing t dis data in setup time 20 ns t dih data in hold time 10 ns t csh cs hold time 20 ns read timing t dod data out delay 80 ns t dohz data out to high impedance delay time for the spi to release the sdo bus 80 ns timing parameters when entering 4-wire spi mode (for determination of clk polarity) t cps clock setup time (clk polarity) setup time of sclk with respect to cs falling edge 20 ns t cphd clock hold time (clk polarity) hold time of sclk with respect to cs falling edge 20 ns t stndy_trigger tx high time from en falling edge to enter into sleep/standby mode 5 cycles www.ams.com/AS8525 revision 2.3 16 - 37 AS8525 datasheet - electrical characteristics 6.3 timing diagrams figure 3. timing diagrams for propagation delays figure 4. timing diagram for duty cycle according to lin 2.1 and j2602 txd bus rxd 50% 50% 50% 50% 95% 5% 0% 100% t df_txd t dr_txd t df_rxd t dr_rxd v bus vth_rec(max) vth_dom(max) vth_rec(min) vth_dom(min) t bus_dom(max) t bus_rec(min) t bus_dom(min) t bus_rec(max) txd t bit t bit lin www.ams.com/AS8525 revision 2.3 17 - 37 AS8525 datasheet - detailed description 7 detailed description the following modules are described in detail under this section: ?? programmable-gain amplifier (pga ) / current-sense amplifier (csa) ?? voltage attenuator ?? voltage regulators (ldo & aldo) ?? lin transceiver ?? temperature monitor/limiter ?? vsup under-voltage reset ?? reset ?? vcc under-voltage reset ?? window watchdog (wwd) ?? timeout watchdog (twd) 7.1 programmable-gain amplifier (pga ) / current-sense amplifier (csa) the current-sense amplifier primarily serves the purpose of shifting the common-mode level of the signal from around the batter y voltage to a low voltage which is nominally half the regulated supply voltage. the input to the amplifier can be optionally chopped for offset a nd low-frequency noise mitigation. as the name indicates, it also provides a programmable gain for the measurement of different battery current ranges which can be programmed through spi. 7.2 voltage attenuator a resistive divider is used as a battery voltage attenuator. like the amplifier, the attenuator can be enabled or disabled thro ugh spi, and in the device standby mode, we additionally need logic high on men pin for enabling. internal reverse polarity protection is provided for vbat pin. figure 5. attenuator implementation 7.3 voltage regulators (ldo & aldo) the device has two low-dropout voltage regulators, named ldo and aldo, with one-time programmable 3.3v / 5v voltage outputs. th e output of the ldo is vcc and that of the aldo is avcc. the regulated voltage choice is common to both the regulators. the regulators a re always on except when the device enters the sleep mode or over-temperature shutdown. the two regulators have inbuilt short-circuit current limitation feature. the regulators can be temporarily shut down for hard reset of th e external circuitry by configuring the device to temporary shu tdown mode through spi. the ldo power-up happens when the por-vsup event occurs (reset_vsup_ n switching from low to high), and the aldo powers up when por-vcc event occurs (reset_vcc_n switching from low to high). the start-up sequ ence is the same even after a temporary shutdow n phase. the aldo will be switc hed off if there is an under-vol tage on vcc, that is, when r eset_vcc_n switc hes back to low. vbat vbat_div vbat_divn pd www.ams.com/AS8525 revision 2.3 18 - 37 AS8525 datasheet - detailed description 7.4 lin transceiver the device has a lin transceiver with slew-controlled bus driver for controlling the electromagnetic emissions from the lin bus . further, the slew rate is independent of the bus load. the transmitter relays the data from the lin controller (tx pin) to the bus (lin pin), and the receiver provides the data on the bus to the controller (rx pin). the transceiver conforms to the lin 2.1 standard. the lin transceiver has a timeout watchdog for tx. after the timeout, the lin bus will be released to the recessive state from the dominant state. the bus driver has an inbuilt short-circuit current limitation fa cility to protect the device from damage when there is a short between the bus and the supply. in addition to the data receiver, there is a low-power receiver active in the device standby/sleep mode which received a wake-u p event from the bus to bring the device to normal mode. 7.5 temperature m onitor / limiter the temperature limiter circuit powers down the device when the junc tion temperature exceeds 170c (nominal). it also issues an over- temperature warning at 160c (nominal). the device is powered up again when the junction temperature falls below 140c (nominal ). the over- temperature warning flag is also cleared at this temperature. the temperature limiter circuit can be optionally disabled through spi. 7.6 vsup under-voltage reset when vsup drops below vsuvr_on, the reset_vsu p_n switches back to low level. this is treated as a master reset and will have th e highest priority over all other signals. in this case, the regulators, lin transceiver, and all other blocks are shut off, and the device comes to a complete stop. the device returns to the normal mode when vsup ri ses over vsuvr_off again irrespective of the mode it was in pr ior to this under-voltage condition. 7.7 reset reset module generates an active-low reset signal for the extern al circuitry supplied by vcc. the behavior of the reset output is depicted in figure 6 in different cases. as shown, reset signa l is affected by an under-v oltage condition on vcc and wa tchdogs which are described in detail in the subsequent sections. the reset period can be one-time programmed to 4, 16, and 32 ms with a default value of 8 ms. figure 6. reset functionality vcc vsup vuvr_off t res t rr t>tj t www.ams.com/AS8525 revision 2.3 20 - 37 AS8525 datasheet - application information 8 application information the AS8525 chip consists of a programmable gain amplifier, a re sistive divider, two low drop-out regulators, and a lin bus tran sceiver. additionally integrated are a reset unit wi th a power-on-reset delay a nd programmable window watchdog a nd timeout wa tchdog time rs. it also includes a watchdog time-out on lin tx node to indicate if the microcontroller is stuck in a loop and the lin bus remains in do minant time for more than the necessary time. 8.1 operating modes and states the device provides four main operating modes ?normal?, ?sleep/stand-by? (programmed by otp), ?temporary shutdown? and ?thermal shutdown?. the lin transceiver can be programmed to operate with lower slew in the normal mode. a detailed state transition table is shown in the following section (see table 16) . 8.1.1 normal mode this is the mode after the power-up. in this mode, voltage regulators, lin transceiver, window watchdog are all active. the pga and resistive divider can be enabled through spi. lin transceiver is capable of sending the tx data from micro-controller to the lin bus at a maximum rate of 20kbps. 8.1.2 standby mode standby mode is a functional low-power mode and is entered by pulling en to ground. the lin transceiver, pga, resistive divider , window watchdog, and tx timeout watchdog circuits are disabled. but, it is possible to selectively enable the voltage and current meas urement paths in this mode using an externally generated measurement enable (men) signal on the men pin. the timeout watchdog can be enabled in this mode to make sure that the microcontroller is active. 8.1.3 sleep mode sleep mode is the current saving mode. the voltage regulators are disabled in this mode. also, the pga, resistive divider, lin transceiver, and the reset and watchdog units are switched off. the lin wake-up circuit and oscillator are active. wake-up is possible only thro ugh remote wake- up through lin pin pulling it to dominant state for 100us. 8.1.4 temporary shutdown mode in this mode, the regulators are powered down and the vcc, avcc are pulled down. this provides an alternative way to reset thos e components powered by AS8525. the feature has to be enabled by an otp bit and can be invoked through spi. the lin transceiver along with t he lin wake-up circuit is powered down. no remote wake-up functionality is possible. lin bus enters into recessive state. the system g oes out of this mode to normal mode after the timeout of an internal timer. 8.1.5 thermal shutdown mode if the junction temperature t j is higher than t sd , the device will be switched into the thermal shutdown mode. the regulators and the transceiver are completely disabled. only the over-temperature monitor is active. as soon as the temperature returns back to t ret , the system enters normal mode. www.ams.com/AS8525 revision 2.3 21 - 37 AS8525 datasheet - application information 8.2 state transition diagram the complete functional state machine of AS8525 is shown in this section. soft states like ?txwd wait? and ?standby wait?, and other wait states have also been included here for completeness. figure 8. finite state machine model of AS8525 reset timeout otp load init0 normal ovtemp temp shut sleep standby por_vsup otp_load t emp s hu td own temp160 temp160 temp160 ! temp160 s t a n d b y standby & sleep rw a ke_ w a it 128msec rwake ! por_vcc reset timeout t e m p s h u t d o w n ! por_vcc || wwdtimeout standby wait txwd_timeout temp160 ! s t a n d b y t e m p s h ut d ow n txwd wait tx=1 t e m p s h u t d o w n temp160 temp160 ! por_vcc rwake temp160 ! por_vcc || wwdtimeout www.ams.com/AS8525 revision 2.3 22 - 37 AS8525 datasheet - application information table 16. transition table transition interface reg. 0x05 d0 flags from mode to mode lin rx tx en rwake uvbat ot uvcc comments normal mode stand-by x-rs x-h 2 h 3 h-l 3 l x x inactive inactive tx is high for t stndy_trigger sleep 1 1. chosen by otp option x-rs x-h 2 h 3 h-l 3 lxxinactiveset tx is high for t stndy_trigger 1 temporary shutdown x-rs x-h 2 xh h 3 x x inactive set the control bit is set through the 4-wire spi interface over- temperature x-rs x-h 2 xx l x x set set temperature monitor output asserted (covered by scan) 2-wire interface x x h-l 3 h-l 3 l x x inactive inactive tx goes high to low within t tx_sp_trigger window. 2-wire interface (this is a testing condition only) normal mode x x x h l x x inactive inactive completion of 2-wire read/write command temporary shutdown x-rs x-h 2 xx h 3 x x inactive set completion of 2-wire write command to 0x05 over- temperature x-rs x-h 2 xx l x x set set temperature monitor output asserted (covered by scan) stand-by mode normal (lw) x h-x 2 x l-h 3 l x x inactive inactive normal (rw) x h-x 2 h x l set x inactive inactive remote wake up event occurred on lin temporary shutdown rs h 2 hl h 3 x x inactive set the control bit is set through the 4-wire spi interface over- temperature rs h 2 hl l x x set set temperature monitor output asserted (covered by scan) temporary shutdown mode normal rs-x h-x 2 xx l x xinactiveclear internal 128ms timer expired over- temperature mode normal rs-x h-x 2 x x l x x clear clear temperature monitor output de-asserted (covered by scan) sleep mode 3 normal rs-x h-x 2 x x l set x inactive clear remote wake up event occurred on lin over- temperature rs h 2 2. effect of transition x x l x x set hold temperature monitor output asserted (covered by scan) all states power off x x x x x x l-h 3 3. cause for transition xx www.ams.com/AS8525 revision 2.3 23 - 37 AS8525 datasheet - application information note: l = low state, h = high state, ot = over-temperature reset, uvcc = under-voltage vcc, uvbat = under-voltage vbat, rwake =remote wake, x = don?t care. 8.3 initialization when the power supply is switched on, when vsup > vsuvr_off, reset_vsup_n beco mes high. this starts the regulator ldo with 3.3v and vuvr_off option of 2.75v. when vcc > vuvr_off (2.75v), active-low porn_2_otp is generated and the regulator aldo is turned on with 3.3v. the rising edge of porn_2_otp loads contents of fuse onto the otp latch after load access time t load . load_otp_in_ prereg signal loads contents of otp latch onto a register. this register provides the actual settings of ldo (and aldo), vuvr_off and reset t imeout period t res . this is done as the otp block is powered by the vcc. if vcc > vuvr_off (phase 2), reset timeout is restarted. reset signal is de- asserted after reset timeout period t res (phase 2) and then device enters into normal mode. the circuit also needs to initialize correctly for very slow ramp rates on vsup (of the order of 0.5v/min). figure 9. initialization sequence for AS8525 table 17. vsup>vsuvr_on and vcc www.ams.com/AS8525 revision 2.3 26 - 37 AS8525 datasheet - application information figure 12. rx interface 8.7 mode input en the AS8525 is switched from normal mode to the standby/sleep mode with a falling edge on en and keeping tx high for t stndy_trigger time. device is switched from standby mode to normal mode with a rising edge at the en pin. the mode change for AS8525 with a falling edge on en can be done independently from the state of the transceiver bus. the device enters into serial port mode by forcing en low and driving tx high to low within t tx_sp_trigger time after en forced to low. this ensures the direct control of device to enter into standby/sleep mode by microcontroller using en pin. figure 13. en pin functionality the en input has an internal active pull down to secure that if this pin is not connected, a low level will be generated. rx vcc AS8525 mcu entry into serial port mode t en_ensclk en rd wr len1 len0 a4 d3 d2 d1 d0 t tx_sp_trigger t tx_su normal mode serial port mode normal mode standby/sleep mode normal mode t tx_hd t stndy_trigger t tx_su tx www.ams.com/AS8525 revision 2.3 27 - 37 AS8525 datasheet - application information figure 14. enable interface if the application doesn?t need the low-power modes of the device, a direct connection of en to vcc is possible. in this case t he AS8525 operates in permanent normal mode. also possible is the external (outside of the module) control of the en line via vsup signal as shown below. figure 15. en connection for permanent normal mode + + vcc reset tx rx en vsup lin vss AS8525 mcu +5v c load v bat c in vbat + + vcc reset tx rx en vsup lin vss AS8525 mcu +5v c load v bat c in www.ams.com/AS8525 revision 2.3 28 - 37 AS8525 datasheet - application information 8.8 4-wire spi interface spi interface is essentially used for programming the gain of the pga, to enable the pga and resistive attenuator in the standb y mode, to temporarily shutdown the ldos, etc. the spi interface can also be used as interface between the AS8525 and an external micro-co ntroller to configure the device and access the status information. the interface is a slave and then only the microcontroller can start th e communication. the spi protocol is very simple and the length of each frame is an integer multiple of byte except when a transmission is start ed. basically each frame has 1 command bits, 5 address/configuration bits, 1 or more data bytes. spi clock polarity settings depend on the value o f the sclk on the cs falling edge. this setting is done on each start of the spi transaction. during the transaction spi clock polarity will be fixed to the settings done. on the cs falling edge the values on sclk signal decide setting of the active spi clock edge for data transfer (see table below). 8.8.1 spi frame a frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an int eger number of bytes. command is coded on the 1 first bit, while address is given on lsb 5 bits (see table below). if the command is read or write, one or more bytes follow. wh en the micro-controller sends more bytes (keeping cs low and sclk toggling), the spi interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses. 8.8.2 write command for write command c0 = 0. after the command code c0 and two reserved bits, the address of register to be written has to be provided from the msb to the l sb. then one or more data bytes can be transferred, always from the msb to the lsb. for each data byte following the first one, used address is the incremented value of the previously written address. each bit of the frame has to be driven by the spi master on the spi clock transfer edge and the spi slave on the next spi clock edge samples it. these edges are selected as per clock polarity settings. in the following figures two examples of write command (without and with address self-increment. table 19. cs and sclk cs sclk description fall low serial data transferred on rising edge of spi clock. sampled at falling edge of spi clock. fall high serial data transferred on falling edge of spi clock. sampled at rising edge of spi clock. any any serial data transfer edge is unchanged. table 20. command bits command bits register address or transmission configuration c0 reserved reserved a4 a3 a2 a1 a0 c0 command www.ams.com/AS8525 revision 2.3 29 - 37 AS8525 datasheet - application information figure 16. protocol for serial data write with length = 1 figure 17. protocol for serial data write with length = 4 8.8.3 read command for read command c0=1. after the command code c0 and two reserved bits, the address of register to be read has to be provided from the msb to the lsb. then one or more data bytes can be transferred from the spi slave to the master , always from the msb to the lsb. to transfer more bytes fro m consecutive addresses, spi master has to keep active the spi cs signal and the spi clock as long as it desires to read data from the slave. each bit of the command and address sections of the frame have to be driven by the spi master on the spi clock transfer edge and the spi slave on the next spi clock edge samples it. each bit of the data section of the frame has to be driven by the spi slave on the spi clock transfe r edge and the spi master on the next spi clock edge samples it. these edges are selected as per clock polarity settings. in the following figures , two examples of read command (without and with address self-increment) have been shown. cs sclk sdi sdo 0 res1 res0 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 transfer edge sampling edge data d7 ? d0 is moved to address a4..a0 here cs sclk sdi sdo 0 r e s 1 a 1 a 4 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 data d7-d0 is moved to address a4-a0 here data d7-d0 is moved to address a4-a0 +1 here data d7-d0 is moved to address a4-a0 +2 here data d7-d0 is moved to address a4-a0 +3 here data d7-d0 is moved to address a4-a0 +4 here a 0 r e s 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 www.ams.com/AS8525 revision 2.3 30 - 37 AS8525 datasheet - application information figure 18. protocol for serial data read with length = 1 figure 19. protocol for serial data read with length = 4 8.8.4 timing in the following figures timing waveforms and parameters are exposed. cs sclk sdi sdo 1 res1 res 0 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 transfer edge sampling edge data d7 ? d0 at address a4..a0 is read here transfer edge sampling edge cs sclk sdi sdo 1 r e s 1 r e s 0 a 4 a 0 a 1 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 data d7-d0 at address a4-a0 is read here data d7-d0 at address a4-a0 +1 is read here data d7-d0 at address a4-a0 +2 is read here data d7-d0 at address a4-a0 +3 is read here data d7-d0 at address a4-a0 +4 is read here www.ams.com/AS8525 revision 2.3 31 - 37 AS8525 datasheet - application information figure 20. timing for writing figure 21. timing for reading 8.9 configuration and diagnostic registers the serial interface can be used for communication between AS8525 and an external microcontroller. the device is only a slave a nd the microcontroller has to initiate the communication. the device can be configured by writing into the control registers and the d iagnostic information can be read out from the diagnostic registers. cs sdi sdo sclk ... ... ... t cps t cphd t dis t dih clk polarity datai datai datai ... t csh t sclkh t sclkl cs sclk sdi sdo t dohz t dod datai datai datao (d7 ) datao (d0) t sclkh t sclkl www.ams.com/AS8525 revision 2.3 32 - 37 AS8525 datasheet - application information 8.9.1 register definitions a total of 32 registers, each of 8-bits which include configuration, diagnostic, and backup are available. the registers can be accessed using the 2-wire or the 4-wire serial interface. table 21 provides a description of all registers. table 21. registers addr register name default value rd/wr description configuration and control registers 0x00 reserved 0x01 reserved 0 x 02 reserved 0 x 03 device configuration register on por_vcc 0000_1100 rd/wr d0 reserved d1 reserved d2 enable/disable over-temperature monitor. (0-disabled, 1-enabled) d3 enable/disable lin transceiver. (0-disabled, 1-enabled) d4- d7 reserved 0 x 04 device control register on por_vsup 0000_0001 rd/wr d0 high slew / low slew control. 1 high slew mode 0 low slew mode d1- d7 reserved 0 x 05 temporary shutdown register on por_vcc 0000_0000 rd/wr d0 temporary shutdown control bit 1 enter temporary shutdown d1- d7 reserved 0 x 06 window watch dog trigger register on por_vcc 0000_0000 wr d0 window watchdog trigger d1 timeout watchdog trigger bit upon a trigger, the bit will be cleared within 2 internal clock cycles. d2- d7 reserved 0 x 07 reserved 0x0a signal path control register on por_vcc 0000_0000 rd/wr d0 reserved d1 enable/disable current channel chopper (0 disabled, 1 enabled) d2 reserved d3 reserved d4 enable/disable voltage attenuator (0 disabled, 1 enabled) d5 enable/disable pga (0 disabled, 1 enabled) d6-d7 pga gain selection 10 00 gain-5, 01 gain-25, 10 gain-50, 11 gain-100 0x0b reserved 0x0c reserved 0x0d reserved 0x0e watchdog timer control register on por_vcc 0000_0000 rd/wr d0 timer resolution 0 1 second, 1 32 seconds d1-d7 timeout period if d0=1, then timeout period = d[7:1]*64*0.512 seconds, else timeout period = d[7:1]*0.512 seconds 0x0f reserved backup registers www.ams.com/AS8525 revision 2.3 33 - 37 AS8525 datasheet - application information 0x10 ??? 0x17 backup-0 ????? backup-7 on por_vsup 0000_0000 rd/wr 8 backup registers these registers can be used by mcu to backup any system configuration before sending the device to sleep mode. if test control register d[5] =1, backup-0 to backup-3 are used for testing connectivity between otp and digital modules. backup-0 = otp[25:32] backup-1 = otp[33:40] backup-2 = otp[41:47] backup-3 = otp[48:49] diagnostic registers 0 x 08 diagnostic register 1 on por_vsup 0000_0011 rd d7-d0 = dr[7:0] 8-lsb bits of the 24-bit diagnostic register. d0 por-vsup (set when vsup < vsuvr_on, cleared after c read) d1 uvvcc under-voltage vcc (set when vcc < vuvr_on, cleared after c read) d2 otemp160 over-temperature reset. (set when temp > t sd , cleared after c read) d3 otemp140 over-temperature warning (set when temp > t otset , cleared after c read) d4 ovvbat overvoltage vbat. (set when vsup > vovthh, cleared after c read) d5 reserved d6 rwake remote wakeup. (set on remote wakeup event on lin bus, cleared after c read) d7 wwdt window watchdog timeout. (set on failure of window watchdog timeout, cleared after c read) 0 x 09 diagnostic register 2 on por_vsup 0000_0000 rd d7-.d0 = dr[15:8] next 8 lsb bits of the 24 bit diagnostic register. d0 txtimeout tx timeout of 1sec. (set on tx low > 1sec, cleared after c read) d1 (tempshut) this bit is set on entering into temporary shutdown state and cleared after c read. d2 set on failure of timeout watchdog trigger, cleared after c read d7- d3 reserved table 21. registers addr register name default value rd/wr description www.ams.com/AS8525 revision 2.3 34 - 37 AS8525 datasheet - package drawings and markings 9 package drawings and markings the devices are available in a 32-pin qfn (5x5) package. figure 22. 32-pin qfn (5x5) package notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters, angle is in degrees. 3. dimension b applies to metallized terminal and is measured between 0.25 and 0.30mm from terminal tip. dimension l1 represen ts ter- minal full back from package edge up to 0.1mm is acceptable. 4. coplanarity applies to the exposed heat slug as well as the terminal. 5. radius on terminal is optional. symbol min typ max a 0.80 0.90 1.00 a1 0.203 ref b 0.18 0.23 0.30 d 5.00 bsc e 5.00 bsc symbol min typ max d1 3.50 3.60 3.70 e1 3.50 3.60 3.70 e 0.50 bsc l 0.30 0.40 0.50 25 32 8 1 16 9 17 24 aywwizz AS8525 3111y www.ams.com/AS8525 revision 2.3 35 - 37 AS8525 datasheet - revision history revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 0.1 oct 20, 2008 mbr initial revision 2.1 nov 02, 2009 mbr updated the entire datasheet according to spec 2.1 2.2 oct 11, 2012 mbr removed ldo 5v option, added section 6.1 characteristics of digital inputs and outputs 2.3 nov 23, 2012 mbr updated section 6.2.1 programmable gain amplifier (pga) dec 31, 2012 sju updated ordering table. www.ams.com/AS8525 revision 2.3 36 - 37 AS8525 datasheet - ordering information 10 ordering information the devices are available as the standard products shown in table 22 . note: all products are rohs compliant and pb-free. buy our products or get free samples online at www.ams.com/icdirect technical support is available at www.ams.com/technical-support for further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor table 22. ordering information ordering code description delivery form package AS8525-aqfp high side current sensor companion ic tape and reel (5000 pcs) 32-pin qfn (5x5) AS8525-aqfm high side current sensor companion ic tape and reel (500 pcs) 32-pin qfn (5x5) www.ams.com/AS8525 revision 2.3 37 - 37 AS8525 datasheet - copyrights copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description rega rding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipien t or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel : +43 (0) 3136 500 0 fax : +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact |
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